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<title>VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register </title></head>
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<h1>VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>EVEX.128.66.0F38.W0 C4 /r VPCONFLICTD xmm1 {k1}{z}, xmm2/m128/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Detect duplicate double-word values in xmm2/m128/m32bcst using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W0 C4 /r VPCONFLICTD ymm1 {k1}{z}, ymm2/m256/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Detect duplicate double-word values in ymm2/m256/m32bcst using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W0 C4 /r VPCONFLICTD zmm1 {k1}{z}, zmm2/m512/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512CD</td>
<td>Detect duplicate double-word values in zmm2/m512/m32bcst using writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F38.W1 C4 /r VPCONFLICTQ xmm1 {k1}{z}, xmm2/m128/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Detect duplicate quad-word values in xmm2/m128/m64bcst using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W1 C4 /r VPCONFLICTQ ymm1 {k1}{z}, ymm2/m256/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Detect duplicate quad-word values in ymm2/m256/m64bcst using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W1 C4 /r VPCONFLICTQ zmm1 {k1}{z}, zmm2/m512/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512CD</td>
<td>Detect duplicate quad-word values in zmm2/m512/m64bcst using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Test each dword/qword element of the source operand (the second operand) for equality with all other elements in the source operand closer to the least significant element. Each element’s comparison results form a bit vector, which is then zero extended and written to the destination according to the writemask.</p>
<p>EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.</p>
<p>EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.</p>
<p>EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VPCONFLICTD</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j*32</p>
<p>IF MaskBit(j) OR *no writemask*THEN</p>
<p>FOR k (cid:197) 0 TO j-1</p>
<p>m (cid:197) k*32</p>
<p>IF ((SRC[i+31:i] = SRC[m+31:m])) THEN</p>
<p>DEST[i+k] (cid:197) 1</p>
<p>ELSE</p>
<p>DEST[i+k] (cid:197) 0</p>
<p>FI</p>
<p>ENDFOR</p>
<p>DEST[i+31:i+j] (cid:197) 0</p>
<p>ELSE</p>
<p>IF *merging-masking* THEN</p>
<p>*DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] ← 0</p>
<p><strong>VPCONFLICTQ</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j*64</p>
<p>IF MaskBit(j) OR *no writemask*THEN</p>
<p>FOR k (cid:197) 0 TO j-1</p>
<p>m (cid:197) k*64</p>
<p>IF ((SRC[i+63:i] = SRC[m+63:m])) THEN</p>
<p>DEST[i+k] (cid:197) 1</p>
<p>ELSE</p>
<p>DEST[i+k] (cid:197) 0</p>
<p>FI</p>
<p>ENDFOR</p>
<p>DEST[i+63:i+j] (cid:197) 0</p>
<p>ELSE</p>
<p>IF *merging-masking* THEN</p>
<p>*DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p> FI</p>
<p>FI</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);</p>
<p>VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);</p>
<p>VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);</p>
<p>VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);</p>
<p>VPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);</p>
<p>VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);</p>
<p>VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);</p>
<p>VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);</p>
<p>VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);</p>
<p>VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);</p>
<p>VPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);</p>
<p>VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);</p>
<p>VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);</p>
<p>VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);</p>
<p>VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);</p>
<p>VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);</p>
<p>VPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);</p>
<p>VPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>EVEX-encoded instruction, see Exceptions Type E4.</p></body></html>